# publications

- D. K.Das, S. Chakraborty and B. B. Bhattacharya, “Irredundant binate realizations of unate functions,”
*International Journal of Electronics,*vol. 25, no. 1, pp. 65-73, 1993. - S. Chakraborty, D. K. Das and B. B. Bhattacharya, “Logical redundancies in irredundant combinational circuits,”
*Journal of Electronic Testing: Theory and Applications,*vol. 25, no. 1, pp. 120-125, 1993. - D. K. Das, U. K. Bhattacharya and B. B. Bhattacharya, “Isomorph redundancy in sequential circuits,”
*IEEE Transactions on Computers*, pp. 992-997, September 2000. - Chakraborty, S. Das, D. K. Das and B. B. Bhattacharya, “Synthesis of symmetric functions for path delay fault testability,”
*IEEE Transactions on Computer-Aided Design*, pp. 1076-1081, September 2000. - Chiiho Sano, Takahiro Mihara, Tomoo Inoue, Debesh K. Das and Hideo Fujiwara, “A partial scan design method for sequential circuits with hold,”
*Transactions on IEICE (DI),*vol. J83, no.9, pp. 981-990, Sep. 2000. (In Japanese). - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count,”
*Journal of Computer Science and Technology,*Springer Science, USA*,*vol. 17, no. 6, pp. 731-737, Nov. 2002 - D. K. Das, S. Chakraborty and B. B. Bhattacharya, “Universal and robust testing of stuck-open faults in Reed-Muller Canonical CMOS circuits,”
*International Journal of Electronics,*vol. 90. no.1, pp. 1-11, January 2003. - H. Rahaman, D. K.Das, and B. B. Bhattacharya, “Testing of stuck-open faults in Generalized Reed Muller and EXOR sum-of-products circuits,”
*IEE Proceeding: Computers and Digital Techniques,*vol. 151, no. 1, pp. 83-91, January 2004. - D. K. Das, S. Ohtake, and H. Fujiwara, “New non-scan DFT techniques to achieve 100% -fault efficiency,”
*Journal of Electronic Testing: Theory and Applications (JETTA),*vol. 20, no. 3, pp. 315-323, 2004. - Y. Zorian, D. K. Das, H. Fujiwara, Y. Li, Y. Min and S. Xu, “Design & Test Education in Asia,”
*IEEE Design & Test of Computers,*pp. 331-338, 2004. - Rahaman, D. K. Das, and B. B. Bhattacharya “A Simple Delay Testable Synthesis of Symmetric Functions,”
*LNCS-3285*, vol. 3285, Springer Verlag, Berlin, pp. 263-270, October 2004. - H. Rahaman, and D. K. Das, “Modeling ESOP Networks for Detecting Multiple Stuck-at Faults,”
*International Journal of AMSE,*France, Vol. 10, No.4, pp.25-36*,*2005*.* - S. Roy, B. K. Sikdar and D. K. Das, “A degree-of-freedom based synthesis scheme for sequential machines with enhanced BIST quality and reduced area,”
*Journal of Electronic Testing: Theory and Applications (JETTA)**,*vol. 21, no. 1, pp. 83-93, 2005. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Implementing Symmetric Functions with Hierarchical Modules for Stuck-at and Path-Delay Fault Testability,”
*Journal of Electronic Testing: Theory and Applications (JETTA) 22: 125-142, 2006, Springer Science, USA.* - H. Rahaman, and D. K. Das, “Testing of Stuck-at and Bridging Faults in Double Fixed-Polarity Reed-Muller (DFPRM) PLA”,
*IEE Computers and Digital Techniques*, Vol.153, No. 2, March 2006. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable Design of Digital Summation Threshold Logic (DSTL) Array for Synthesis of Symmetric functions,”
*International Journal of Computer Applications, ACTA press,*pp. 115-123, Volume 29, No. 2, 2007. - H.Rahaman, D. K. Das, and B. B. Bhattacharya, “An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Complex Cell,”
*IEEE Transactions on Instrumentation and Measurement,*Vol. 57, No. 12, pp.2838-2845, December 2008. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable Design of AND-EXOR Logic Networks with Universal Tests for Detecting Stuck-at and Bridging Faults,”
*International Journal of Computers and Electrical Engineering (Elsevier),*vol. 35, issue 5, pp.644-658, September 2009. - H. Rahaman, D. Kole, D. K. Das, and B. B. Bhattacharya, “On the Detection of Bridging Fault in Reversible Circuits”,
*The IUP Journal of Computer Sciences,*vol. IV, no.4, 28-41, October 2010. - Hafizur Rahaman, Dipak K. Kole, Debesh K. Das, and Bhargab B. Bhattacharya,
*“*Fault Diagnosis for Missing-Gate Fault (SMGF) Model in Reversible Quantum Circuits,”*International Journal of Computers and Electrical Engineering (Elsevier)**,*vol. 37, issue 4, pp. 475-485, July 2011. - Dipak K. Kole, Hafizur Rahaman, Debesh K. Das, and Bhargab B. Bhattacharya, “Derivation of test set for detecting multiple missing-gate faults in reversible circuits,”
*International Journal of Computers and Electrical Engineering (Elsevier),*vol. 39,issue 2, pp. 225-236 February, 2013. - Arighna Deb, Debesh K Das and Susmita Sur Koley, “ A Modular Design to Synthesize Symmetric Functions using Quantum Quaternary Logic,”
*Journal of Low Power Electronics*, vol. 10, no. 3, pp. 443-454, 2014. - Debesh K Das and Hideo Fujiwara, “One More Class of Sequential Circuits having Combinational Test Generation Complexity,”
*Journal of Electronic Testing: Theory and Applications,*vol. 31, issue 3, pp. 321-327, June 2015. - Arindam Banerjee and Debesh K. Das, “The design of reversible signed multiplier using ancient Indian mathematics.,”
*Journal of Low Power Electronics*, vol. 11, no. 4, pp.467-478, 2015. - Arindam Banerjee and Debesh K. Das, “A New Squarer Design with Reduced Area and Delay,”
*IET Computers and Digital Techniques*, vol. 10, no. 5, pp. 205 – 214, september, 2016. - Arighna Deb, Debesh K Das, Hafizur Rahaman, and Bhargab B. Bhattacharya, Robert Willie and Rolf Drechsler, “Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability,”
*ACM Journal on Emerging Technologies in Computing Systems,*Volume 12(4):34, June 2016. - Arighna Deb and Debesh K Das, “An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata”,
*Microprocessors and Microsystems,*53 (2017), pp. 157-167, 2017. - Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das, “Approach of genetic algorithm for power-aware testing of 3D IC. IET Computers & Digital Techniques 13(5): 383-396, 2019.
- Bappaditya Mondal, Chandan Bandyopadhyay, Dipak Kumar Kole, Debesh Kumar Das & Hafizur Rahaman, “Test Generation from Boolean Generator for Detection of Missing Gate Faults (MGF) in Reversible Circuit Using Boolean Difference Method,”
*IETE Journal of Research*, July 2019 - Joyati mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman and Debesh Kumar Das, “Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits
__,__” Journal of Circuits, Systems and Computers, 28(12): 1950212, 2019. - Tanusree Kaibartta, G. P. Biswas, and Debesh Kumar Das, “Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs”
*Journal of Electronic Testing: Theory and Applications,*vol. 36, issue 2, February 2020. - Subrata Das, Debesh Kumar Das, and Soumya Pandit, “A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects, Journal on Emerging Technologies in Computing Systems,” Accepted, 2020
- Arindam Banerjee and Debesh K. Das, “A novel ALU circuit based on reversible logic,” Journal of Circuits, Systems and Computers, Accepted, 2020.
- H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Universal Test Set for Detection of Stuck-at Faults in GRM (Generalized Reed-Muller) Circuits,” in
*Progress in**VLSI Design and Test*(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 351-360, 2003. - D. K. Das, and B. B. Bhattacharya, “Redundancy and Undetectability of Faults in Logic Circuits: A Tutorials,” in
*Progress in**VLSI Design and Test*(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 514-526, 2004. - H. Rahaman, D. K. Das, and B. B. Bhattacharya: Synthesis and testing of reversible logic circuits – A survey, in
*Progress in**VLSI Design and Test*(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 71-80, 2005. - H. Rahaman, D. K. Kole, D. K. Das, and B. B. Bhattacharya: Detection of bridging faults in reversible circuits, in
*Progress in**VLSI Design and Test*(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 384-392, August 2006. - D. K. Das and B. B. Bhattacharya, “Testable design of non-scan sequential circuits using extra logic,” in
*Proceedings of the IEEE Asian Test Symposium,*pp. 176-182, 1995. - D. K. Das and B. B. Bhattacharya, “Does retiming affect redundancy in sequential circuits?” in
*Proceedings of the 9*pp. 260-263, 1996.^{th}IEEE International Conference on VLSI Design, - D. K. Das, U. K. Bhattacharya and B. B. Bhattacharya, “Isomorph redundancy in sequential circuits,” in
*Proceedings of the 14*pp. 463-468, USA, 1996^{th}IEEE VLSI Test Symposium, - D. K. Das, S. Chakraborty and B. B. Bhattacharya, “New BIST techniques for detecting CMOS stuck-open faults,” in
*Proceedings of the 10*pp. 303-308, 1997.^{th}IEEE International Conference on VLSI Design, - D. K. Das, S. Chakraborty and B. B. Bhattacharya, “Universal and robust testing of stuck-open faults in Reed-Muller Canonical CMOS circuits,” in
*Proceedings of 3*pp. 259-268, 1997.^{rd}International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (REED-MULLER 97), - D. K.Das, I. Chaudhury and B. B. Bhattacharya, “Design of an optimal test pattern generator for built-in self testing of path delay faults” in
*Proceedings of the 11*pp. 205-210, 1998.^{th}IEEE International Conference on VLSI Design, - D. K. Das, S. Chakraborty and B. B. Bhattacharya, “Interchangeable boolean functions and their effects on redundancy in logic circuits,” in
*Proceedings of the IEEE Asia and South Pacific Design Automation Conference,*pp. 469-474, Japan, 1998. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “An adaptive BIST to detect multiple stuck-open faults in CMOS circuits,” in
*Proceedings of the IEEE Asia and South Pacific Design Automation Conference,*Hong Kong, pp. 287-290, January 1999. - S. Chakraborty, S. Das, D. K. Das and B. B. Bhattacharya, “Synthesis of symmetric functions for path delay fault testability,” in
*Proceedings of the 12*1999.^{th}IEEE International Conference on VLSI Design, - D. K. Das, S. Ohtake, and H. Fujiwara, “New DFT techniques of non-scan sequential circuits with complete fault efficiency,” in
*Proceedings of the IEEE Asian Test Symposium,*pp. 263-268, China, 1999. - B. Sikdar, D. K. Das, and B. B. Bhattacharya, “Fixed spectral coefficients to detect multiple stuck-at faults in combinational circuits,” in
*Proceedings of 4*Victoria, Canada, pp. 133-137,1999.^{th}International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (REED-MULLER 99), - D. K. Das, S. Chakraborty and B. B. Bhattacharya, “Boolean algebraic properties of fault behavior in logic circuits, ” in
*Proceedings of the**4*Germany, pp. 143-150, September, 2000.^{th}International Workshops on Boolean Problems, - T. Inoue, D. K. Das, C. Sano, T. Mihara, and H. Fujiwara, “Test generation and design-for-testability based on acyclic structure with hold registers,”
*Digest of IEEE 2000 Int. Workshop on RTL ATPG & DFT (WRTLT2000),*pp. 1-10, Sept. 2000. - T. Innoue, D. K. Das, C. Sano, T. Mihara and H. Fujiwara, “Test generation of acyclic sequential circuits with hold registers,” in
*Proceedings of the IEEE/ACM International Conference on Computer-Aided Design*November, pp. 550-556, U. S. A., 2000. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Transition Count based BIST for Detecting Multiple Stuck-Open Faults in CMOS Circuits,” in
*Proceedings of The 2*Korea, pp. 307-310, August, 2000.^{nd}IEEE Asia-Pacific Conferences on ASICs (AP-ASIC 2000), - D. K. Das, B. B. Bhattacharya, S. Ohtake, and H. Fujiwara, “Testable design of sequential circuits with improved fault efficiency,” in
*Proceedings of the 14*pp. 128-131, 2001.^{th}IEEE International Conference on VLSI Design, - B. Sikdar, P. Majumdar, M. Mukherjee, N. Ganguly, D. K. Das and P. Pal Chaudhury, “Hierarchial cellular automata as on-chip test pattern generator,” in
*Proceedings of the 14*pp. 403-408, 2001.^{th}IEEE International Conference on VLSI Design, - B. Sikdar, D. K. Das, V. Boppana, C. Yang, S. Mukherjee and P. Pal Chaudhury, “GF(2
^{p}) Cellular automata as a built in self test structure,” in*Proceedings of the IEEE Asia and South Pacific Design Automation Conference,*pp. 319-324, Japan, January 2001. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Universal and robust testing of stuck-open faults in GRM and ESOP circuits,” in
*Proceedings of 5*USA, 2001.^{th}International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (REED-MULLER 01), - S. Roy, B. K. Sikdar, M. Mukherjee and D. K. Das, “Enhancing BIST Quality of Sequential Machines Through Degree-of-freedom Analysis,” in
*Proceedings of the IEEE Asian Test Symposium,*pp. 263-268, Japan, 2001. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “A new synthesis of symmetric functions,” in
*Proceedings of the 15*pp. 160-165, 2002.^{th}IEEE International Conference on VLSI Design and Asia and South Pacific Design Automation Conference (VLSI-ASPDAC 2002), - S. Roy, B. K. Sikdar, M. Mukherjee and D. K. Das, “Degree-of-freedom analysis for sequential machines targeting BIST quality and gate area,” in
*Proceedings of the 15*pp. 671-676, 2002.^{th}IEEE International Conference on VLSI Design and Asia and South Pacific Design Automation Conference (VLSI-ASPDAC 2002), - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “A Simple Delay-Testable Design of Digital Summation Threshold Logic (DSTL) Array,
**”**in*Proceedings of the*5Germany, September, 2002.^{th}International Workshops on Boolean Problems, - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Mapping symmetric functions to hierarchical modules for delay testablity,
**”***Proceedings of the IEEE Asian Test Symposium,*China, November 2003. - Pradipta Maji, Chandrama Shaw, Rishi Nandi, Debesh K Das, P. Pal Chaudhuri, “Design of a Cellular Automata Based Pattern Classifier,”
*Proceedings of 2*India, December, 2003^{nd}International Conference on Applied Artificial Intelligence, - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Easily testable realizations of ESOP networks for detecting stuck-at and bridging faults,
**”***Proceedings of the IEEE International Conference on VLSI Design,*pp. 487-492, January 2004. - H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable design of GRM networks for detecting stuck-at and bridging faults,
**”***Proceedings of the IEEE Asia and South Pacific Design Automation Conference,*Japan, pp. 224-229, January 2004. - H. Rahaman and D. K. Das, “A simple delay testable synthesis of symmetric functions,
**”***Proceedings of the IEEE Asian Applied Computing Conference, Nepal in October,2004*. - D. K. Das, T. Innoue, S. Chakraborty and H. Fujiwara, “Max-testable class of sequential circuits having combinational test generation complexity,”
*Proceedings of**IEEE Asian Test Symposium,*Taiwan, pp. 342-347, November 2004. - Rahaman and D. K. Das, “Bridging fault detection in double fixed polarity Reed-Muller (DFPRM) PLA,
**”**in*Proceedings of IEEE Asia and South Pacific Design Automation Conference,*Japan, vol. 1/2, page 172-177, 2005. - S. Roy, B. K. Sikdar, and D. K. Das, “Cellular automata based test structures with logic folding,
**”***IEEE International Conference on VLSI Design,*January 2005. - B.K. Sikdar, A. Sarkar, S. Roy and D.K. Das, “Synthesis of testable finite state machine through decomposition,”
*IEEE Asian Test Symposium,*India, December 2005. - H. Rahaman and D. K. Das, “Double Fixed-Polarity Reed-Muller (DFPRM) Design with universal test set of lower length,”
*7*Tokyo, 2005.^{th}International Symposium on Representations and Methodology of Future Computing Technologies (RM2005), - H. Rahaman, B. K. Sikdar, and D.K. Das, “Synthesis of Symmetric Boolean Functions Using Quantum Cellular Automata”,
*International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS 06),*pp.119-124, Tunis, Tunisia**.** - H. Rahaman, D. Kole, D. K. Das, and B. B. Bhattacharya, “Optimum Test Set for Bridging Faults Detection in Reversible Circuits”,
*IEEE Asian Test Symposium 2007, pp.125-128*. - H. Rahaman, D. Kole, D. K. Das, and B. B. Bhattacharya, “On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set”, in
*Proceedings of**International Conf. on VLSI Design*2008, pp. 163-168. - Dipak K. Kole, H. Rahaman, D. K. Das, and B. B. Bhattacharya, “A Constructive Algorithm for Synthesis of Reversible Logic Circuits”, in
*Proceedings of ICIT 2009,*pp.23-28. - Dipak K. Kole, H. Rahaman, Debesh K Das and Bhargab B. Bhattacharya, “Optimal Reversible Logic Circuits Synthesis based on a Hybrid DFS-BFS Technique”, in
*Proceedings of**IEEE International Symposium on Electronic Design (ISED 2010)*pp 208-212, India, December, 2010. - Dipak K. Kole, H. Rahaman, Debesh K Das and Bhargab B. Bhattacharya, “Derivation of Optimal Test set for Detection of Multiple Missing-Gate Faults in Reversible Circuits’, in
*Proceedings of**IEEE Asian Test Symposium (ATS 2010),*Shanghai, pp.33-38, November, 2010. - Dipak K. Kole, H. Rahaman, Debesh K Das and Bhargab B. Bhattacharya,, “Detection of Multiple Missing-Gate Faults in Reversible Circuits”, in
*Proceedings of**Intl. workshop on Reversible Computation,*pp. 117-124, Germany, July 2010. - Dipak K. Kole, H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Synthesis of Online Testable Reversible Circuit”, in
*Proceedings of**13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems , DDECS2010,*pp.277-280, Austria, April 2010. - Surajit K. Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, and Hafizur Rahaman, “Test Architecture Design for TSV based 3D Stacked ICs using Hard SOCs,” in
*Proceedings of**the IEEE East-West Design & Test Symposium (EWDTS),*Ukraine, September, 2011. - Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das and Hafizur Rahaman, “Optimization of Test Wrapper for TSV Based 3D SOCs”, in
*Proceedings of**the IEEE International Symposium on Electronic Design (ISED 2011)*, pp.188-193, 2011. - Dipak Kole, Hafizur Rahaman, Debesh K Das and Bhargab B. Bhattacharya “Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits”,
*IEEE International Symposium on Electronic Design (ISED 2011)*, pp. 200-205, 2011. - Debesh K. Das, Subhrajit Sinha Roy, A. Dmitiriev, A. Morozov, and M. Gössel, “Constraint Don’t cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes,” in
*Proceedings of the**10*Freiberg, Germany, September, 2012, pp. 33-40.^{th}International Workshops on Boolean Problems, - Joyati Mondal, Debesh K. Das, Dipak K. Koley, and Hafizur Rahaman, “A Design for Testability Technique for Quantum Reversible Circuits,” in
*Proceedings of**the IEEE East-West Design & Test Symposium (EWDTS),*Ukraine, September, 2012, pp. 249-252. - M. Pradhan, C. Giri, H. Rahaman, and D. K. Das, “An Algorithm for Core-Based Test Time Optimization for 3-D Integrated Circuits”, The Thirteenth IEEE Workshop on RTL and High-Level Testing, 22-23 November, 2012, Niigata, Japan.
- Papiya Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das and Bhargab B. Bhattacharya, “Reversible Logic Circuits Synthesis using Genetic Algorithm and Particle Swarm Optimization,”
*Proceedings of**IEEE International Symposium on Electronic Design (ISED 2012)*, 2012, pp. - Joyati Mondal, Debesh K. Das, Dipak K. Koley, and Hafizur Rahaman, “Design for Testability Techniques for Quantum Reversible Circuits,”
*4*Pune, January, 2013.^{th}IEEE International Workshop on Reliability Aware System Design and Test, - Arighna Deb, Debesh K Das, Hafizur Rahaman and Bhargab B. Bhattacharya, “Reversible synthesis of symmetric Boolean functions based on unate decomposition,”
*IEEE International Conference GLSVLSI,*2-4 May,2013, Paris, France. - Arighna Deb, Debesh K Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Willie and Rolf Drechsler, “Reversible circuit synthesis of symmetric functions using a simple regular structure,”
*5*4-5 July, 2013, Victoria, Canada.^{th}IEEE International Conference on Reversible Computing, - Joyati Mondal, Debesh K. Das, Dipak K. Koley, Hafizur Rahaman anf Bhargab B Bhattacharya “On Designing Testable Reversible Circuits Using Gate Duplication,”
*17th IEEE International Symposium on VLSI Design and Test,*27-30 July, 2013, Jaipur, India. - M. Pradhan, C. Giri, H. Rahaman, and D. K. Das,, “Optimal Stacking of SOCs in a 3D-SIC for Post-Bond Testing,”
*IEEE International Conference on 3D System Integration (3D IC),*October, 2013, San Francisco, USA. - M. Pradhan, C. Giri, H. Rahaman, and D. K. Das,, “Optimizing Test Time for Core-based 3-D Integrated Circuits by a Technique of Bi-partitioning,”
*IEEE East-West Design & Test Symposium (EWDTS),*Rostov-on-Don, Russia, September, 2013. - Arighna Deb, Debesh K Das and Susmita Sur Koley, “ Modular Design for Symmetric Functions using Quantum Quaternary Logic,”
*IEEE International Symposium on Electronic Design (ISED 2013)*, Singapore2013. - Arindam Banerjee and Debesh K Das, “The Design of Reversible Multiplier using Ancient Indian Mathematics,”
*IEEE International Symposium on Electronic Design (ISED 2013)*, Singapore, 2013. - Debesh K Das, Rupali Mitra, and Bhargab B Bhattacharya, “A Functional Approach to Robust Testability of Path-Delay Faults in Two-Level Circuits,”
*5*Mumbai, January, 2014.^{th}IEEE International Workshop on Reliability Aware System Design and Test, - Joyati Mondal and Debesh K Das, “Analogy between Quantum Reversible Circuit and Digital Logic with Respect to Test Generation,”
*5*Mumbai, January, 2014.^{th}IEEE International Workshop on Reliability Aware System Design and Test, - Debesh K Das, Debabani Chowdhury, Bhargab B Bhattacharya, and Tsutomu Sasao, “Inadmissible Class of Boolean Functions under Stuck-at Faults,”
*Proceedings of**IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL 2014)*, Bremen, Germany, pp. 237-242, May 2014. - Rupali Mitra, Debesh K Das and Bhargab B Bhattacharya, “On Designing Robust Path-Delay Fault Testable Combinational Circuits based on Functional Properties”
*IEEE Computer Society Annual Symposium on VLSI,*Tampa, Florida, pp. 202-207, 9-11 July 2014. - Arindam Banerjee and Debesh K Das, “Efficient Squaring in Reversible Logic using Reduced Garbage and Ancillary Inputs,”
*6*10-11 July, 2014, Kyoto, Japan.^{th}IEEE International Conference on Reversible Computing, - Arighna Deb and Debesh K Das, “A Regular Network of Symmetric Functions in Quantum-Dot Cellular Automata,”
*18th IEEE International Symposium on VLSI Design and Test,*16-18 Coimbatore, India, 1-6, July, 2014. - P Dasgupta, P Dasgupta and Debesh K Das, “A Novel Algorithm for Interconnect-aware Two-level Optimization of Multi-output SOP functions,”
*Proceedings of**11*Freiberg, Germany, September, pp. 219-226, 2014.^{th}International Workshop on Boolean Problems, - Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das and Hafizur Rahaman, “Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method,”
*Proceedings of The 23*China, November 16-19, pp. 68-73, 2014.^{rd}IEEE Asian Test Symposium, - Arindam Banerjee and Debesh K Das, “Squaring in Reversible Logic using Iterative Structure,”
*IEEE East-West Design & Test Symposium (EWDTS),*Kiev, Ukraine, 1-4, September, 2014. - Arighna Deb, Debesh K Das and Bhargab B Bhattacharya, “Synthesis of Symmetric Boolean Functions Using a Three-Stage Network,”
*Proceedings of IEEE International Symposium on Electronic Design (ISED 2014)*, NITK, Mangalore, India, pp. 182-186, December 2014. - Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman and Debesh Kumar Das, “Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits,”
*13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems , DDECS2015,*22-24 April, 2015, Belgrade, Serbia. - A. Deb, R. Wille, R. Drechsler, and D. K. Das, “An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization,” in
*IEEE 45th International Symposium on Multiple-Valued Logic (ISMVL 2015)*, Canada, May 2015. - Sabyasachee Banerjee, Subhashis Majumder and Debesh K. Das, “Partitioning-based Test Time Reduction for Core-Based 3DICs,”
*IEEE International Symposium on VLSI Design and Test,*26-29 June, 2015, Ahmedabad, India. - Arindam Banerjee and Debesh K. Das, “Squarer Design with Reduced Area and Delay,”
*IEEE International Symposium on VLSI Design and Test,*26-29 June, 2015, Ahmedabad, India. - Tanusree Kaibarta and Debesh K. Das, “Optimizing Test Time for Core-Based 3-D Integrated Circuits by Genetic Algorithm,”
*6*August, 2015, Kualalumpur, Malayasia.^{th}Asia Symposium on Quality Electronic Design (ASQED 2015), - Joyati Mondal, Debesh Kumar Das and Bhargab B Bhattacharya, “Design-for-Testability in Reversible Logic Circuits based on Bit-Swapping,”
*The 24*Mumbai, November 23-25, 2015.^{th}IEEE Asian Test Symposium, - Tanusree Kaibarta and Debesh K. Das, “Testing of 3D IC with minimum power using Genetic Algorithm,”
*10th IEEE International Design & Test Symposium (IDT’15),*Jordan, December 14-16, 2015. - Arindam Banerjee and Debesh K. Das, “Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs,”
*Proceedings of the IEEE International Conference on VLSI Design,*Kolkata, January 4-6, 2016. - Subrata Das, Soma Das, Adrija Majumdar, Parthasarathi Dasgupta and Debesh Kumar Das, “Delay estimates for Graphene nanoribbons: a novel measure of fidelity and experiments with global routing trees,”
*IEEE International Conference GLSVLSI,*18-20 May, 2016, Boston, USA. - Debabani Chowdhury, Debesh K Das, Bhargab B Bhattacharya, and Tsutomu Sasao, “On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults,”
*IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL 2016)*, Sapporo, Japan, May 2016. - Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh,and Debesh Kumar Das, “A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits,
*14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems , DDECS2016,*22-24 April, 2016, Belgrade, Serbia. - Debasis Pal,Abir Pramanik, Parthasarathi Dasgupta and Debesh Kumar Das, “Double Patterning Lithography (DPL)-Compliant Layout Construction (DCLC) with Area-Stitch Usage Tradeoff”,
*IEEE International Symposium on VLSI Design and Test,*24-27 May, 2016, IIT Guwahati, India. - Debabani Chowdhury, Debesh K Das, Bhargab B Bhattacharya, and Tsutomu Sasao, “On the Properties of Root-Functions in Logic Circuits,”
*Proceedings of**12*Freiberg, Germany, September, 2016.^{th}International Workshop on Boolean Problems, - Archi Bhattacharya and Debesh Kumar Das, “Recognition of Ragas of Hindustani Music Played on Harmonium,”
*22*Baripada, Orissa, India, November, 2016.^{nd}International Symposium on Frontiers of Research in Speech and Music (FRSM) 2016, - Arindam Banerjee and Debesh K Das, “A New ALU Architecture Design using Reversible Logic,”
*Proceedings of IEEE International Symposium on Embedded Computing and System Design (ISED 2016)*, Patna, India, December 2016. - Joyati Mondal and Debesh K Das, “Design for testability technique of reversible logic circuit based on exclusive testin,”
*8*^{th}*IEEE International Workshop on Reliability Aware System Design and Test,*Mumbai, January, 2017. - Subrata Das, and Debesh K. Das, “A Technique to Construct Global Routing Trees for Graphene Nanoribbon (GNR
**),”***The 18*Santa Clara, USA, March 2017.^{th}International Symposium on Quality Electronic Design (ISQED 2017), - Joyati Mondal and Debesh K Das, “Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing,”
*The 26*Taiwan, November 27-30, 2017.^{th}IEEE Asian Test Symposium, - Archi Bhattacharya and Debesh Kumar Das, “ Do Traditional Arabic Music and Hindustani Classical Music have Same Root?”
*23*NIT Rourkela, December, 2017.^{rd}International Symposium on Frontiers of Research in Speech and Music (FRSM) 2017, - Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma and Debesh K. Das, “A Placement Optimization Technique for 3D IC”
*7th International Symposium on Embedded Computing and System Design,*NIT Durgapur, December 2017. - Subrata Das and Debesh K Das, “Steiner Tree Construction for Graphene Nanoribbon Based Circuits in Presence of Obstacles,”
*IEEE International Symposium on Devices, Circuits and Systems (ISDCS 2018),*IIEST Shibpur, 29-31 March, 2018 - Subrata Das and Debesh K Das, “Floorplanning in Graphene Nanoribbon (GNR) Based Circuits,”
*IEEE Computer Society Annual Symposium on VLSI,*Hong Kong, 9-11 July 2018. - Tanusree Kaibarta and Debesh K. Das, “Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach,”
*IEEE International Symposium on VLSI Design and Test,*June 28-30, 2018, Madurai, India. - Arindam Banerjee and Debesh Kumar Das, “Arithmatic Circuits using Reversible Logic: A Survey Report,”
*6th International Doctoral Symposium on Applied Computation and Security Systems (ACSS-2019),*Kolkata, March 2019. - Archi Bhattacharya and Debesh Kumar Das, “A Study of the Raga Zeelaf and its Relationship with Arabian Traditional Music,”
*24th International Symposium on Frontiers of Research in Speech and Music (FRSM) 2019,*Kanpur, July, 2019. - Sayantani Roy, Debesh Kumar Das and Arighna Deb, “Delay efficient all-optical carry lookahead adder,”
*IEEE International Symposium on VLSI Design and Test,*July 2019, IIT Indore, India. - Subrata Das, Soumya Pandit, Debesh Kumar Das, “Crosstalk Aware Global Routing of Graphene Nanoribbon Based Circuits,”
*IEEE International Conference on Nanotechnology,*Macau, July 2019. - Arighna Deb and Debesh Kumar Das, “Detailed Fault Model for Physical Quantum Circuits,”
*The 28*, December 10-13, 2019.^{th}IEEE Asian Test Symposium, Kolkata, India